rev. pre feb 2004 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a preliminary technical data ADG3308 preliminary technical data one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 analog devices, inc., 2004 low voltage 1.2 v to 5.5 v, bidirectional, logic level translators functional block diagram features bidirectional level translation operates from 1.2 v to 5.5 v low quiescent current <5 a applications spi tm , microwire tm and i 2 c tm translation low voltage asic level translation smart card readers cell phones & cell-phone cradles portable communication devices telecommunicatons equipment network switches and routers storage systems (san/nas) computing/server applications gps portable pos systems low cost serial interfaces general description the ADG3308 is an 8-channel bidirectional level transla- tor. its function is to provide level shifting in a multi- voltage system. the voltage applied to v cca sets up the logic levels on the a side of the device, while v ccy sets the levels on the y side. in this way, signals applied to the v cca side of the device appear as v ccy compatible logic on the other side of the device and vice versa as the device is designed to handle bidirectional signals. the device is guaranteed for operation over the supply range 1.2 v to 5.5 v. these devices are suited to applications like data transfer between a low voltage dsp/controller and a higher voltage device. other applications include high end consumer products where constant changes to the chipset desgins result in multiple supply levels in the application. v ccy operates from +1.65 to 5.5 v while v cca from +1.2 to v ccy . v cca must always operate from a supply that is lower than v ccy . when the device enable pin (en) is pulled low, the ax and yx inputs/outputs are tri-stated. the en pin is driven high for normal operation. en pin is referred to v ccy voltage. product highlights 1. bidirectional level translation. 2. the ADG3308 is fully guaranteed from 1.2 v to 5.5 v supply range. 3. 20 lead tssop and lfcsp (4mm x4mm) packages. a1 y1 gnd v ccy v cca a8 y8 a7 y7 a6 y6 a5 y5 a4 y4 a3 y3 a2 y2 en
?2? rev. pre ADG3308?specifications 1 preliminary technical data parameter symbol conditions min typ 2 max units logic inputs/outputs input high voltage v ih v ccy -0.4 v v cca -0.4 v input low voltage v il 0.4 v 0.4 v output high voltage v oh i oh = 20 a, v ccy -0.4 v i oh = 20 a, v cca -0.4 v output low voltage v ol i ol = 20 a, 0.4 v i ol = 20 a, 0.4 v input leakage current i i 0 v in 3.6 v 1 a output leakage current i o 0 v in 3.6 v 1 a input capacitance 3 c in f = 1 mhz, v a/y = v cca/y or gnd 5 pf output capacitance 3 c o f = 1 mhz, v a/y = v ccy/a or gnd 5 pf switching characteristics 3 3.3v 0.3v v cca v ccy 5v 0.5v propagation delay, t pd y - a r s = 50 ? , c a = 15 pf 5 ns a - y r s = 50 ? , c y = 50 pf 5 ns rise time t r_y r s = 50 ? , c y = 50 pf 5 ns fall time t f_y r s = 50 ? , c y = 50 pf 5 ns rise time t r_a r s = 50 ? , c a = 15 pf 5 ns fall time t f_a r s = 50 ? , c a = 15 pf 5 ns maximum data rate r s = 50 ? , c y = 50 pf, c a = 15 pf 40 mbps channel to channel skew t skew r s = 50 ? , c y = 50 pf, c a = 15 pf tbd ns part to part skew t ppskew r s = 50 ? , c y = 50 pf, c a = 15 pf tbd ns 1.8v 0.15v v cca v ccy 3.3v 0.3v propagation delay, t pd y - a r s = 50 ? , c a = 15 pf 10 ns a - y r s = 50 ? , c y = 50 pf 15 ns rise time t r_y r s = 50 ? , c y = 50 pf 10 ns fall time t f_y r s = 50 ? , c y = 50 pf 10 ns rise time t r_a r s = 50 ? , c a = 15 pf 10 ns fall time t f_a r s = 50 ? , c a = 15 pf 10 ns maximum data rate r s = 50 ? , c y = 50 pf, c a = 15 pf 35 mbps channel to channel skew t skew r s = 50 ? , c y = 50 pf, c a = 15 pf 5 ns 1.2v 0.1 v v cca v ccy 3.3 0.3 v propagation delay, t pd y - a r s = 50 ? , c a = 15 pf 20 ns a - y r s = 50 ? , c y = 50 pf 20 ns rise time t r_y r s = 50 ? , c y = 50 pf 15 ns fall time t f_y r s = 50 ? , c y = 50 pf 15 ns rise time t r_a r s = 50 ? , c a = 15 pf 15 ns fall time t f_a r s = 50 ? , c a = 15 pf 15 ns maximum data rate r s = 50 ? , c y = 50 pf, c a = 15 pf 20 mbps channel to channel skew t skew r s = 50 ? , c y = 50 pf, c a = 15 pf 5 ns 2.5v 0.2v v cca v ccy 3.3v 0.3v propagation delay, t pd y - a r s = 50 ? , c a = 15 pf 8.5 ns a - y r s = 50 ? , c y = 50 pf 8.5 ns rise time t r_y r s = 50 ? , c y = 50 pf 8.5 ns fall time t f_y r s = 50 ? , c y = 50 pf 8.5 ns rise time t r_a r s = 50 ? , c a = 15 pf 8.5 ns fall time t f_a r s = 50 ? , c a = 15 pf 8.5 ns maximum data rate r s = 50 ? , c y = 50 pf, c a = 15 pf 40 mbps channel to channel skew t skew r s = 50 ? , c y = 50 pf, c a = 15 pf 10 ns power requirements power supply voltages v ccy 1.65 5.5 v v cca 1.1 5.5 v quiescent power supply current i ccy digital inputs = 0 v or v ccy 5a i cca digital inputs = 0 v or v cca 5a notes 1 temperature range is as follows: b version: ?40c to +85c. 2 all typical vlaues are at t a = +25c unless otherwise stated. 3 guaranteed by design, not subject to production test. specifications subject to change without notice. (v ccy = +1.65 to 5.5 v, v cca = +1.1 to v ccy , gnd = 0 v, all specifications t min to t max unless otherwise noted)
ADG3308 ?3? rev. pre preliminary technical data absolute maximum ratings 1 (t a = 25c unless otherwise noted) v cc y to gnd . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 v to +7 v v cc a to gnd . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 v to +7 v digtal inputs (a) . . . . . . . . . . . . . . -0.3 v to (v cc a +0.3v) digtal inputs (y) . . . . . . . . . . . . . . -0.3 v to (v cc y +0.3v) en to gnd . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 v to +7 v operating temperature range industrial (b version) . . . . . . . . . . . . . . ?40c to +85c storage temperature range . . . . . . . . . ?65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . 150c 20 lead tssop ja thermal impedance . . . . . . . . . . . . . . . . . . . . 143c/w 20 lead lfcsp - 4 layer board ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 32c/w lead temperature, soldering (10seconds) . . . . . . . 300c ir reflow, peak temperature (<20 seconds) . . . +235c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADG3308 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide model temperature range package description package option ADG3308bru ?40c to +85c tssop ru-20 ADG3308bcp ?40c to +85c lfcsp cp-20 warning! esd sensitive device 12 y8 9 11 gnd 10 13 y7 en 8 ADG3308 (not to scale) va a1 a2 a5 a6 1 2 3 4 5 20 14 y6 vy a7 a8 6 7 15 16 17 18 19 y1 y2 y3 y4 y5 a3 a4 pin configuration 20 lead tssop (ru-20) 20 lead 4mmx4mm lfcsp (cp-20) pin 1 indicator top view ADG3308 1 a2 2 a3 3 a4 4 a5 5 a6 a7 6 a8 7 en 8 gnd 9 y8 10 15 y3 14 y4 13 y5 12 y6 11 y7 20 a1 19 vcca 18 vccy 17 y1 16 y2
ADG3308 ?4? rev. pre preliminary technical data general description the ADG3308 level translator allows the required level shifting necessary for data transfer in a system where mul- tiple voltages are used. the device requires two supplies, v cca and v ccy . these supplies set the logic levels on each side of the device. the device translates data present on the v a side of the device to the higher voltage level at the v y side of the device. similarly, as the device is ca- pable of bidirectional translation, data applied to the v y side will be translated to the voltage referenced to v a . power supplies the voltage applied to v cca must always be less than or equal to v ccy . while en is low, the v cca supply may be removed, and both a and y i/o?s will remain tri-stated. level translator architecture the forward channel consists of a string of inverters and a level translator, while the reverse channel consists simply of inverters. a level translator is not required in the re- verse path (y-a) as the supply voltage v ccy must always be greater than or equal to v cca . a current limiting resis- tor is used in series with each channel to prevent any con- tention issues, see figure 1.
figure 1. simplified functional diagram of one channel. as the driven side has to drive a load capacitance through this 6k resistance, one shot generators are used to drive large mos devices in the output stage to help speed up the rate of switching. the output stage is inactive and three state except when transistions are present on either side of the translator. when this happens the one shot fires turn- ing on the output stage and driving the load capacitance faster than if it were driven through the resistor. as the device is bi-directional, both input stages will be active during this period. while this design gives maximum speed from the device, it can result in some current driv- ing back into the source driving the input of the translator. to ensure correct operation, the input driver should meet the following requirements - 50 ? maximum output im- pedance with minimum of 20ma output current when driving 20mbps. enable operation when pulled low, the en input allows the user to tri-state both sides (a and y) of the level translator. en pin is referred to v ccy voltage.
ADG3308 ?5? rev. pre preliminary technical data outline dimensions dimensions shown in inches and (mm). 20-lead tssop (ru-20) 20 11 10 1 0.260 (6.60) 0.252 (6.40) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pi n 1 sea t i n g pl a n e 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 o 0 o 20-lead lfcsp (cp-20) 1 20 5 6 11 16 15 bottom view 10 0.080 (2.25) 0.083 (2.10) sq 0.077 (1.95) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.030 (0.75) 0.024 (0.60) 0.020 (0.50) 0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.080 (2.00) ref 0.010 (0.25) min 0.020 (0.50) bsc 12 o max 0.008 (0.20) ref 0.028 (0.70) max 0.026 (0.65) nom 0.002 (0.05) 0.0004 (0.01) 0.0 (0.0) 0.035 (0.90) max 0.033 (0.85) nom seating plane controlling dimensions are in millimeters pin 1 indicator top view 0.148 (3.75) bsc sq 0.157 (4.0) bsc sq
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